TAIPEI, Nov. 27, 2025 /PRNewswire/ — As Moore’s Law slows, advanced packaging has become the critical lever driving breakthroughs in AI chip performance, according to DIGITIMES chief semiconductor analyst Tony Huang. Speaking with DIGITIMES Asia, Huang emphasized that heterogeneous integration is now as pivotal to system performance as transistor scaling once was.
Without advanced packaging, moving from 28nm to A16 would deliver roughly an 80-fold increase in compute density per reticle area, Huang said. With it, the gain rises to around 320 times.
Bottlenecks driving innovation
He explained that AI workloads have exposed multiple technical bottlenecks—what he calls the new “walls”: the memory wall, addressed through high-bandwidth memory (HBM); the I/O and communication walls, tackled by reducing latency through chiplet and interposer technologies; the power and thermal walls, mitigated through power efficiency and thermal management; and the yield and fabrication walls, eased by smaller chiplets with higher yields.
Technologies such as 3D SoC stacking, hybrid bonding, and co-packaged optics (CPO) are now key enablers, he added.
Market growth outpacing the semiconductor industry
Huang forecasts that advanced packaging for AI data center chips will grow at a compound annual rate of 45.5% from 2024 to 2030, far outpacing the overall semiconductor industry’s 8.7% and the broader packaging and testing sector’s 9.5%.
“2.5D CoWoS-type solutions still dominate and will account for more than half of the total market,” he said. “Their share will gradually decline from 69% to 58% as 3D and hybrid approaches mature.”
He noted that the industry is transitioning from 2.5D to 3.5D packaging, citing AMD’s MI300X AI accelerator, which combines 3D SoIC and 2.5D CoWoS and is manufactured by TSMC. Broadcom is also developing a 3.5D accelerator using a face-to-face structure, he said.
Taiwan’s dominant position
“Taiwanese companies accounted for about 77% of the global data center AI packaging market in 2024,” Huang said. “Even with intensifying competition from Intel, Samsung, and new US and Chinese ecosystems, Taiwan’s share is expected to stay near 70% by 2030.”
If HBM assembly—still primarily done in South Korea—is excluded, Taiwan’s market share reached 90% in 2024, he added.
Defining the landscape
Huang noted that DIGITIMES defines data center AI chips in three categories: AI server CPUs; AI accelerators, including GPUs from NVIDIA and AMD, and custom AI chips like Google’s TPU and AWS Trainium; and AI networking chips such as switch ICs from Broadcom and DPUs from NVIDIA.